CS4382A-DQZ【PDF 30/50 页】IC DAC 8CH 114DB 192KHZ 48-LQFP

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DS618F2

CS4382A

6.3.2

Single Volume Control (SNGLVOL)

Default = 0

0 - Disabled

1 - Enabled

Function:

The individual channel volume levels are independently controlled by their respective Volume Control

Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume

Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.

6.3.3

Soft Volume Ramp-Up After Error (RMP_UP)

Default = 0

0 - Disabled

1 - Enabled

Function:

An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional

Mode. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft

and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed

in these instances.

Notes:

For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.

6.3.4

Mutec Polarity (MUTEC+/-)

Default = 0

0 - Active High

1 - Active Low

Function:

The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default), the MUTEC

pins are high when active. When set to 1 the MUTEC pin(s) are low when active.

Note:

During reset the MUTEC output pins are high impedance and the external mute circuitry will need

to be self biased into an active state, see Section 4.11. Once reset has been released, the MUTEC out-

puts’ active polarity will be set by this bit.

6.3.5

Auto-Mute (AMUTE)

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam-

ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is

done independently for each channel. The quiescent voltage on the output will be retained, and the Mute

Control pin will go active during the mute period. The muting function is affected, similar to volume control

changes, by the Soft and Zero Cross bits in the Mode Control 3 register.

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